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QL-EOS-S3-breakout

Pinout guide

A breadboard-friendly, low part count breakout board for the QuickLogic EOS-S3 ARM/FPGA IC.

The goals of this project are:

  • Low-cost, minimum viable ARM+FPGA design that is breadboard compatable
  • Footprint, power, UART pin compatibility with Teensy 3.2.
  • All pins on Bank A placed in a group, because they can have their IO voltage set with a reference
  • Bootstrap, SPI flash, and reset pins placed in non-breadboardable location to avoid inadvertant interference with application circuit
  • Pins with multiple IO functions preferred over FPGA only pins
  • Pins in understandable (ascending) order by FPGA IO number, when possible

See the release PDF for the schematic.

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